CY8C20236A PSoC? Functional Overview

CY8C20236A PSoC? Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■ The Core
■ CapSense Analog System
■ System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20x36A/66A PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 GPIO are also included. The GPIO
provides access to the MCU and analog mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS,
8-bit Harvard-architecture microprocessor.

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Features
■ Automotive Electronics Council (AEC) Q100 qualified
■ Operating Range: 1.71 V to 5.5 V
■ Low power CapSense
?
 block
? Configurable capacitive sensing elements
? Supports SmartSense
? Supports a combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
■ Powerful Harvard-architecture processor
? M8C CPU speed can be up to 24 MHz or sourced by an
external crystal, resonator, or clock signal
? Low power at high speed
? Interrupt controller
? Temperature range: –40 °C to +85 °C
■ Flexible on-chip memory
? Two program/data storage size options:
? CY8C20x36A: 8 KB flash/1 KB SRAM
? CY8C20x66A: 32 KB flash/2 KB SRAM
? 1,000 flash erase/write cycles
? Partial flash updates
? Flexible protection modes
? In-system serial programming (ISSP)
■ Precision, programmable clocking
? Internal main oscillator (IMO): 6/12/24 MHz ± 5%
? Internal low speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
? Precision 32 kHz oscillator for optional external crystal
■ Programmable pin configurations
? Up to 36 general-purpose I/Os (GPIOs) (depending on
package)
? Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
? 25-mA sink current on each GPIO
? 120 mA total sink current on all GPIOs
? Pull-up, high Z, open-drain modes on all GPIOs
? CMOS drive mode – 5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
? 20 mA  total source current on all GPIOs
? Selectable, regulated digital I/O on port 1
? Configurable input threshold on port 1
? Hot-swap capability on all Port 1 GPIO
■ Versatile analog mux
? Common internal analog bus
? Simultaneous connection of I/O
? High power supply rejection ratio (PSRR) comparator
? Low-dropout voltage regulator for all analog resources
■ Additional system resources
? I
2
C Slave:
? Selectable to 50 kHz, 100 kHz, or 400 kHz
? No clock stretching (under most conditions)
? Implementation during sleep modes with less than 100 μA
? Hardware address validation
? SPI master and slave: Configurable 46.9 kHz to 12 MHz
? Three 16-bit timers
? Watchdog and sleep timers
? Internal voltage reference
? Integrated supervisory circuit
? 8 to 10-bit incremental analog-to-digital converter (ADC)
? Two general-purpose high speed, low power analog
comparators
■ Complete development tools
? Free development tool (PSoC Designer?)
? Full-featured, in-circuit emulator (ICE) and programmer
? Full-speed emulation
? Complex breakpoint structure
? 128 KB trace memory
■ Package options
? CY8C20x36A:16-Pin 3 × 3 × 0.6 mm QFN
? CY8C20x66A: 48-Pin SSOP

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Features
 True Dual-Ported memory cells which enable simultaneous
access of the same memory location
 Flow-through and Pipelined devices
 32 K × 9 organizations (CY7C09179V)
 64 K × 8 organizations (CY7C09089V)
 128 K × 8/9 organizations (CY7C09099V/199V)
 3 Modes
 Flow-through
 Pipelined
 Burst
 Pipelined output mode on both ports enables fast 100 MHz
operation
 0.35-micron CMOS for optimum speed and power
 High speed clock to data access 6.5
[1]
/7.5
[1]
/9/12 ns (max.)
 3.3 V low operating power
 Active = 115 mA (typical)
 Standby = 10 ?A (typical)
 Fully synchronous interface for easier operation
 Burst counters increment addresses internally
 Shorten cycle times
 Minimize bus noise
 Supported in Flow-through and Pipelined modes
 Dual Chip Enables for easy depth expansion
 Automatic power down
 Commercial and Industrial temperature ranges
 Available in 100-pin TQFP
 Pb-free packages available

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The FLEx18? family includes 2-Mbit, 4-Mbit, and 9-Mbit
pipelined, synchronous, true dual port static RAMs that are high
speed, low power 3.3 V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. The result of writing to the same location by more than
one port at the same time is undefined. Registers on control,
address, and data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0
 or LOW on CE1
 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted  is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for  message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833V device in this family has limited features. See
Address Counter and Mask Register Operations on page 7 for
details.

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Features
 True dual-ported memory cells which allow
simultaneous access of the same memory location
 32K x 16 organization (CY7C027V/027AV
[1]
)
 64K x 16 organization (CY7C028V)
 32K x 18 organization (CY7C037AV)
 64K x 18 organization (CY7C038V)
 0.35 micron Complementary metal oxide semiconductor
(CMOS) for optimum speed and power
 High speed access: 15, 20, and 25 ns
 Low operating power
 Active: ICC = 115 mA (typical)
 Standby: ISB3
= 10 ?A (typical)
 Fully asynchronous operation
 Automatic power-down
 Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
 On-chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Separate upper-byte and lower-byte control
 Dual chip enables
 Pin select for Master or Slave
 Commercial and Industrial temperature ranges
 100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin
TQFP

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The Quadport Datapath Switching Element (DSE) family offers
four ports that may be clocked at independent frequencies
from one another. Each port can read or write up to 133 MHz
[]
,
giving the device up to 10 Gb/s of data throughput. The device
is 1-Mb (64K × 18) in density. Simultaneous reads are allowed
for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed.
Any port can write to a certain location while other ports are
reading that location simultaneously, if the timing spec for port
to port delay (tCCS) is met. The result of writing to the same
location by more than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
tCD2
 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address the counter will self-increment the address internally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0
 or LOW on CE1
 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430CV (64K × 18 device) supports burst contains
for simple array partitioning. Counter enable inputs are
provided to stall the operation of the address input and utilize
the internal address generated by the internal counter for fast
interleaved memory applications. A port’s burst counter is
loaded with an external address when the port’s Counter Load
pin (CNTLD) is asserted LOW. When the port’s Counter
Increment pin (CNTINC) is asserted, the address counter will
increment on each subsequent LOW-to- HIGH transition of
that port’s clock signal. This will read/write one word from/into
each successive address location until CNTINC is deasserted.
The counter can address the entire switch array and will loop
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter. A counter-mask register is used to control the
counter wrap. The counter and mask register operations are
described in more details in the following sections.
The counter or mask register values can be read back on the
bidirectional address lines by activating MKRD or CNTRD,
respectively.
The new features included for the QuadPort DSE family
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, readback of mask register value on address
lines, interrupt flags for message passing, BIST, JTAG for
boundary scan, and asynchronous Master Reset.

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Features
 True dual-ported memory cells that allow simultaneous
access of the same memory location
 16K x 36 organization (CY7C056V)
 32K x 36 organization (CY7C057V)
 0.25-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed/power
 High-speed access: 12/15 ns
 Low operating power
 Active: ICC = 250 mA (typical)
 Standby: ISB3
= 10 ?A (typical)
 Fully asynchronous operation
 Automatic power-down
 Expandable data bus to 72 bits or more using Master/Slave
Chip Select when using more than one device
 On-chip arbitration logic
 Semaphores included to permit software handshaking
between ports
 INT flag for port-to-port communication
 Byte select on left port
 Bus matching on right port
 Depth expansion via dual chip enables
 Pin select for Master or Slave
Commercial and Industrial temperature ranges
 Available in 144-Pin Thin quad plastic flatpack (TQFP) or
172-Ball ball grid array (BGA)
 Pb-free packages available
 Compact packages:
 144-Pin TQFP (20 x 20 x 1.4 mm)
 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)