CY8C20236A Additional System Resources

CY8C20236A Additional System Resources
System resources provide additional capability, such as I
2
C
slave, SPI master, or SPI slave interfaces, three 16-bit
programmable timers, and various system resets supported by
the M8C.
These system resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. The merits of each system
resource are listed here:
■ The I
2
C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■ The I
2
C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■ The I
2
C enhanced slave interface appears as a 32-byte RAM
buffer to the external I
2
C master. Using a simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For usage
details, refer to the application note I2C Enhanced Slave
Operation - AN56007.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for
capacitive sensing.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.